1. Field of the Invention
The present invention relates to a data repeating apparatus (or data transfer apparatus) which is applied to a local area network and the like wherein digital data sandwiched by delimiters are to be transferred.
2. Prior Art
In general, a local area network (i.e., LAN) can be defined as the communication network which is occupied by a single communication system. Herein, the data communication is performed in a bit-serial manner among the interdevices mutually linked together by the above network. There are two kinds of the LAN systems, i.e., the ring network and bus network.
In the ring network as shown in FIG. 1, plural terminals 72 are linked together in a ring by means of a transmission line 71. Herein, a signal sent from a certain terminal is reproduced by its adjacent terminal, and then it is repeated and transferred to the next terminal. Thus, this signal is sequentially transferred through some terminals, and finally it is returned back to the original terminal. Normally, all of the terminals are equally related to each other. Therefore, the transmission line 71 is commonly used by those terminals by the time-sharing control, which enables the data transfer between the certain terminals.
The serial data as shown in FIG. 2 is transferred in the above-mentioned ring network. This serial data normally contains a token and a frame. Herein, the token represents a right to access the transmission line, while the frame represents information to be transferred through the transmission line. In each of the token and frame, its significant data is sandwiched by delimiters 73 as Illustrated by the shadow portions in FIG. 2. This delimiter 73 is used for identifying the significant data, and it is embodied by the data consisting of two bits or more. Further, there is provided a preamble 74 between two data, wherein this preamble (i.e., invalid-bit portion) corresponding to the predetermined number of bits is eventually sandwiched by the delimiters. In the meantime, there are two methods how to access the token. According to one method, one terminal which picks up the token so as to receive the frame is now operating to collect the frame which circulates through the transmission line once and then returns back thereto, while this terminal simultaneously sends out the token to the transmission line. According to another method, the terminal releases and sends out the token to the transmission line Just after transferring the frame.
In the above-mentioned ring network, a specific station has a stabilized sending-clock generator activated by a crystal oscillator, while another repeating station directly uses the receiving clock as its sending clock. In other words, when observing this network with respect to the clock system, there is established a master-slave relationship. Such technique is disclosed in Japanese Patent Laid-Open Publication Nos. 58-150346 and 60-226249, for example.
However, when sending the data by use of the receiving clock, the number of the repeating stations must be limited in order to maintain a relatively high receiving/sending precision, or a high-precision receiving/sending circuitry must be required for the repeating station in response to the number of the necessary repeating stations. In this case, it may be possible to convert the receiving data synchronized with the receiving clock into another data synchronized with the sending clock without changing the serial-data configuration of the receiving data as disclosed by U.S. Pat. No. 4,674,086 (see FIG. 10 of this patent). However, such data conversion leads the circuit configuration to be complicated.
The above-mentioned U.S. patent also discloses the conventional method how to extract the delimiter from the receiving serial data and then produce a delimiter timing signal. According to this method, the receiving serial data is once serially stored in the memory and the like, and then it is subjected to the data checking operation. For example, when the delimiter is four-bit data of which binary code is represented by "1010", as shown in FIG. 3, the receiving serial data is entered into a shift register 81, by which the bit pattern of the delimiter is detected by a decoder 82 so as to produce the delimiter timing signal.
The above-mentioned circuitry which produces the delimiter timing signal as shown in FIG. 3 has a relatively simple configuration. However, when the transfer rate of the serial data becomes high or the length of the delimiter becomes longer, the hardware configuration of this circuitry eventually becomes more complicated. Further, since the decoder contains the multi-input gate circuits such as the AND circuit and OR circuit and these circuits contains the delay elements, it is difficult to form the hardware of this circuitry which can perform the high-speed operations. If the terminal cannot perform the high-speed data processings, the period of time by which the data circulates through the transmission line once and then returns back to the original terminal must become longer, which deteriorates the performability of the network.